A connection between a conductive region of an impurity diffused layer in a semiconductor substrate or a lower level wiring and an upper level wiring layer through a contact hole formed in an interlayer insulating film is one of the more important fabrication techniques in a semiconductor device. As the degree of the integration density of integrated circuit device increases, contact openings formed in the insulating layer are required to have a small opening size to ensure a high density device. In order to increase alignment margins between contact openings and overlying conductors, it is necessary that the critical dimension of the contact openings be reduced.
A conventional method for forming a contact in a semiconductor device is schematically illustrated in FIGS. 1A and 1B. Referring to FIG. 1A, an insulating layer 2 is formed on a semiconductor substrate (not shown). The insulating layer 2 is etched to form contact holes 4 that expose conductive regions of a semiconductor substrate. A conductive material 6 such as doped polysilicon as for a storage node is deposited on the resulting structure. Through conventional photolithographic process, the polysilicon layer 6 between the contact holes 4 is etched to form storage nodes 6a that are electrically connected to conductive region of the semiconductor substrate as shown in FIG. 1B. However, there are some problems with this method. If misalignment occurs during the photolithographic process, the polysilicon may be over-etched at the neck part (see reference numeral 7) of the storage node 6b and in severe case, the storage node 6b may fall down.
Another conventional contact in a semiconductor device is schematically shown in FIGS. 3 and 4. FIG. 3 schematically shows top plan views of bit line patterns and FIG. 4 is a cross-sectional view of bit line pattern and contact plug taken along line A-A' of FIG. 3. In FIG. 3, in order to increase alignment margins between bit lines 16a and 16c and bit line contacts (see reference number 14 of FIG. 4), portions of the bit line patterns are formed to have enlarged portions (see reference number 17) at regions where contact is to be made. Such enlarged portions 17 may be a serious obstacle to smaller feature size. Also an electrical bridge between adjacent bit line patterns may occur.